word size


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word size

(processor)
The number of bits that a CPU can process at one time. Processors with many different word sizes have existed though powers of two (8, 16, 32, 64) have predominated for many years. A processor's word size is often equal to the width of its external data bus though sometimes the bus is made narrower than the CPU (often half as many bits) to economise on packaging and circuit board costs.
This article is provided by FOLDOC - Free Online Dictionary of Computing (foldoc.org)

word size

The size of the CPU's internal registers. For example, a 32-bit computer has a 32-bit word size. See word.
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References in periodicals archive ?
The findings showed varying sensitivity and specificity values according to the verbal stimulus used (Table 2): the larger the phrase or word, the higher the specificity of the test, while the smaller the word size the higher the sensitivity.
JsSandbox can detect whether the JavaScript is obfuscated or not, using the word size. Because most obfuscated strings are very long, the maximum word size of the parameter in the target function can be calculated.
Another is the use of 4-bit word sizes in lieu of the standard 16.
Based on the results in Section 3.2, a window size of 7 and context word size of 200 are used in all of the following experiments.
A 31-bit word size accounts for at least 2.1 billion (2.1 x [10.sup.9]) samples without overflowing any counter.
Hence, for m [is less than or equal to] w, being w the word size in bits of the computer used, we have an O(n) time algorithm using O(}[Sigma]}) extra space and O(m + }[Sigma]}) preprocessing time, where [Sigma] denotes the alphabet.
Commercially available integrated-circuit components limited the word size to 257 bits.
The number of bits, called CPU word size, made the chips slow by today's standards.
Conventional LUT size increases with the input word size. The product word is stored in location [X.sub.i] for 0 [less than or equal to] [X.sub.i] [less than or equal to] [2.sup.L] - 1.
In SHA-384/512, the word size is double that of SHA-224/256.
Results show that the proposed parallel architecture is more compact than the loop architecture and has a linear increase in area consumption with respect to word size. However, the area of the loop implementation increases exponentially with the word size, which has a strong impact on the length of its critical path.