write-back


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Related to write-back: write-through cache, Cache hit

write-back

(memory management)
A cache architecture in which data is only written to main memory when it is forced out of the cache.

Opposite of write-through. See also no-write allocation.
References in periodicals archive ?
Web-based budgeting, with direct write-back, is the latest substantial addition and development of the modern, comprehensive suite of tools that offers immediate ROI for users at all levels.
Write-back caching is a function that is enabled by the inclusion of small cache memory components within the disk drive electronics.
Data written to a write-back cache is vulnerable until it is made permanent on disk, which is done later as a background task when spare cycles are available.
These features include real-time consolidations, Web-based write-back to a variety of OLAP and SQL repositories, executive dashboard, workflow with automated alerts as well as interactive ad hoc slice and dice analysis.
Alphablox exceeded both the required basic and advanced capabilities including stringent testing of MDX support, calculated members, cube write-back, exporting to Excel, and multiple hierarchies support.
For added system performance, the PowerPC 440 includes dynamic branch prediction, 24 DSP instructions, and non-blocking caches that can be managed in either a write-through or write-back mode.
Advances in embedded core architectures, such as multiple busses, split transactions, write-back buffers, and streaming cache fills have increased the effort required to develop a Seamless Processor Support Package (PSP).
8m(a)) arises, mainly due to a write-back through the P&L account of goodwill previously written off against reserves, together with fixed asset write-downs and the costs of the transaction.
0 released last year by providing support for Microsoft's XP and XP Embedded Operating Systems as well as incorporating additional enhancements to image size limitations, dynamic write-back filtering, power management support, simplified installation and web-based product delivery and licensing.
To provide high performance, the LH7A400 integrates a 200MHz ARM922T core (ARM9TDMI(TM), 8KB Instruction Cache, 8KB Data Cache, MMU, Write-Back Buffer) with a processing speed of about 220 Million Instructions Per Second (MIPS).