VHDL

Very High Speed Integrated Circuit (VHSIC) Hardware Description Language. A large high-level VLSI design language with Ada-like syntax. The DoD standard for hardware description, now standardised as IEEE 1076.

["VHSIC Hardware Description Language", M.R. Shahdad et al, IEEE Computer 18(2):94-103 (Feb 1985)].

This article is provided by FOLDOC - Free Online Dictionary of Computing (foldoc.org)

VHDL

(VHSIC Hardware Description Language) A hardware description language (HDL) used to design electronic systems at the component, board and system level. VHDL allows models to be developed at a very high level of abstraction. Initially conceived as a documentation language only, most of the language can today be used for simulation and logic synthesis. VHDL became the IEEE 1076 standard in 1987, but was initially developed for the U.S. military's VHSIC program in 1981. See Verilog and RTL.

HDL Languages

VHDL and Verilog are the most popular HDLs. These examples show a circuit described in RTL in both languages and the resulting schematic of the gate level netlist created after synthesis (below). (Language and schematic examples from "HDL Chip Design" courtesy of Douglas J. Smith.)

Copyright © 1981-2025 by The Computer Language Company Inc. All Rights reserved. THIS DEFINITION IS FOR PERSONAL USE ONLY. All other reproduction is strictly prohibited without permission from the publisher.

Mentioned in

References in periodicals archive

The Section III describes the VHDL implementation of PAELib: components that monitors switching activity, static power and occupied area; creation of power&area aware gate models; creation of higher function circuits (counter, shift registes, etc.) with power and area estimation.

PAELib: A VHDL Library for Area and Power Dissipation Estimation of CMOS Logic Circuits

Input Sum B A OPV3 OPV5 OPV7 0 0 -169 mV -183 mV -295 mV 0 1 179 mV 190 mV 295 mV 1 0 183 mV 193 mV 295 mV 1 1 -195 mV -206 mV -195 mV Input Carry B OPV3 OPV5 OPV7 0 -293 mV -295 mV -299 mV 0 -264 mV -267 mV -298 mV 1 -264 mV -267 mV -298 mV 1 157 mV 170 mV 295 mV Figure 3: A short description of VHDL code of the framework, (a) inverter circuit implemented using the MOLFET device, (b) FBE model, and (c) TSB model description.

VHDL-AMS Simulation Framework for Molecular-FET Device-to-Circuit Modeling and Design

The whole design is translated to VHDL with the C[lambda]aSH tool, to do register Transfer Level (RTL) simulation by using the automatically generated VHDL models of the static part, RMs, reconfigurable regions, and their interfacing logic.

Modelling and Assertion-Based Verification of Run-Time Reconfigurable Designs Using Functional Programming Abstractions

Very High Speed Integrated Circuits Hardware Description Language (VHDL) is used to describe hardware in terms of software.

APPROACH TO PERFORM COMBINATIONAL DIVIDER BASED FLOATING POINT CALCULATIONS USING VHDL COMPONENT

La ecuacion 2, sera descrita en VHDL para su representacion circuital, definien do los componentes para la implementacion de los correspondientes factores, donde la reduccion modular, A(x) mod p(x), sera realizada bajo la arquitectura de un circuito LFSR, como el mostrado en la Figura 1.

CESR-Codificador RS (255,k) eficiente para sistemas reconfigurables

void master_frame_interrupt_handle () { node_number++; if (slave_node_number >= SLAVE-COUNT) } slave_node_number = 2; } arm_set_main_frame_flag (TRUE); arm_send_main_frame_data (node_number); } ALGORITHM 2: VHDL code on the FPGA system.

Modeling a heterogeneous embedded system in coloured petri nets

Implementation equations (16) and 17) of PI controller in FPGA using VHDL needs to be written in discrete time form as FPGA is a digital device.

An FPGA based controller for a SOFC DC-DC power system

The proposed architecture was implemented in VHDL using Xilinx ISE 10.1.

Performance Analysis of a Flexible, Optimized and Fully Configurable FPGA Architecture for Two-Channel Filter Banks

The complex multipliers and complex adders are implemented in hardware using VHDL [11].

Adaptive VLSI architecture of beam former for active phased array radar

Side-by-side examples of SystemVerilog and VHDL compare the ways each language can be used in the design of digital systems.

Digital design and computer architecture, 2d ed